The present invention relates to a method for fabricating a semiconductor device, in which a plug or inlaid interconnect is formed by a single or dual damascene process.
Recently, various methods of forming an inlaid interconnect for a semiconductor device by a single or dual damascene process have been researched and developed.
Hereinafter, a known method of fabricating a semiconductor device by a single damascene process (which will be herein called a xe2x80x9cfirst prior art examplexe2x80x9d for convenience sake) will be described with reference to FIGS. 20(a) through 20(d).
First, as shown in FIG. 20(a), an insulating film 11, which may be either an SiO2 film or a film with a dielectric constant lower than that of an SiO2 film, is deposited over a semiconductor substrate 10. Next, as shown in FIG. 20(b), an etch stopper film 12 with insulation properties, which may be an Si3N4 film, for example, is deposited over the insulating film 11.
Then, as shown in FIG. 20(c), a resist pattern 13 is defined on the etch stopper film 12. And the insulating film 11 is plasma-etched using the resist pattern 13 as a mask, thereby forming an opening 14 that passes through the stopper and insulating films 12 and 11 as shown in FIG. 20(d). The opening 14 will be used as a via hole or interconnection groove. If the resist pattern 13 disappears as a result of the plasma etching process, then the etch stopper film 12 will be a hard mask.
Subsequently, the resist pattern 13 is stripped by an ashing process using oxygen plasma, and then the inner faces of the opening 14 are cleaned. Thereafter, although not shown, a metal film is deposited over the substrate to fill in the opening 14 and then parts of the metal film, which are exposed on the stopper film 12, are removed by a chemical/mechanical polishing (CMP) process, for example. In this manner, a plug or inlaid interconnect is formed inside the opening 14.
Hereinafter, another known method of fabricating a semiconductor device by a dual damascene process (which will be herein called a xe2x80x9csecond prior art examplexe2x80x9d for convenience sake) will be described with reference to FIGS. 21(a) through 21(d) and 22(a) through 22(c).
First, as shown in FIG. 21(a), a first insulating film 21, which may be either an SiO2 film or a film with a dielectric constant lower than that of an SiO2 film, is deposited over a semiconductor substrate 20. Next, a first etch stopper film 22 with insulation properties, which may be an Si3N4 film, for example, is deposited over the first insulating film 21.
Then, as shown in FIG. 21(b), a second insulating film 23, which may be either an SiO2 film or a film with a dielectric constant lower than that of an SiO2 film, is deposited over the first etch stopper film 22. Next, as shown in FIG. 21(c), a second etch stopper film 24 with insulation properties, which may be an Si3N4 film, for example, is deposited over the second insulating film 23.
Subsequently, as shown in FIG. 21(d), a first resist pattern 25 with an opening 25 a for via hole is defined on the second etch stopper film 24. And the second etch stopper film 24, second insulating film 23, first etch stopper film 22 and first insulating film 21 are plasma-etched using the first resist pattern 25 as a mask, thereby forming a via hole 26 as shown in FIG. 22(a).
Thereafter, as shown in FIG. 22(b), a second resist pattern 27 with an opening 27a for interconnection groove is defined on the second stopper film 24. And the second etch stopper film 24 and second insulating film 23 are plasma-etched using the second resist pattern 27 as a mask, thereby forming an interconnection groove 28 as shown in FIG. 22(c). Subsequently, the second resist pattern 27 is stripped, by an ashing process using oxygen plasma, and then the inner faces of the via hole 26 and interconnection groove 28 are cleaned.
Then, although not shown, a metal film is deposited over the substrate to fill in the via hole 26 and interconnection groove 28 and then parts of the metal film, which are exposed on the second etch stopper film 24, are removed by a CMP process, for example. In this manner, a dual damascene metallization structure is obtained.
The single damascene process of the first prior art example, however, has the following drawbacks. Specifically, when the resist pattern 13 is stripped by the ashing process using oxygen plasma, a damaged layer 15 is formed by the oxygen plasma on the inner walls of the insulating film 11 (i.e. parts the film 11 surrounding the opening 14) as shown in FIG. 23(a). In addition, the insulating film 11 is deformed and partially lost. In other words, the inner walls of the opening 14 in the insulating film 11 are dented inward unintentionally. As a result, the diameter (or diameter) of the opening 14 exceeds a predetermined value, i.e., the diameter of the opening of the etch stopper film 12.
To eliminate the process step of stripping the resist pattern 13 by the ashing process using the oxygen plasma, the resist pattern 13 may be removed by over-etching the insulating film 11 in the plasma etching process.
However, if the insulating film 11 is over-etched, then the following problems will newly arise.
First, if the insulating film 11 is either an inorganic insulating film or an organic/inorganic hybrid film, a CFC etching gas is normally used to plasma-etch the insulating film 11. Thus, if the over-etching process is performed for a long time, then a Teflon (polytetrafluoroethylene) film is formed on the inner walls of the opening 14. In that case, an ashing process should be performed for a long time or intensely to remove the Teflon film.
As a result of such an intense ashing process, a damaged layer will be formed in the insulating film 11, e.g., on the inner walls or on the bottom of the opening 14, or the insulating film 11 will be partially deformed. For example, the inner walls of the opening 14 might be partially etched, away and deformed into a bowed shape. Particularly when the insulating film 11 is an organic/inorganic hybrid film, the damaged layer, which will be formed around the opening 14 of the insulating film 11, adversely increases the dielectric constant.
Next, if the insulating film 11 is an organic insulating film, then the insulating film 11 is normally plasma-etched using a gas containing oxygen or a mixture of nitrogen and hydrogen gases as the etching gas. However, if the over-etching process is performed for a long time using a gas containing oxygen as the etching gas, then the insulating film 11 will be partially deformed (i.e., the inner walls of the opening 14 will be dented inward). Or the damaged layer will be formed around the inner walls of the opening 14 to increase the dielectric constant unintentionally. On the other hand, if a mixture of nitrogen and hydrogen gases is used as the etching gas, then normally the inner walls of the opening 14 will not be dented so much as the process where the oxygen-containing gas is used. However, if the over-etching process is performed for a long time, then the insulating film 11 will also be partially deformed (i.e., the inner walls of the opening 14 will also be dented noticeably) or the damaged layer will also be formed around the inner walls of the opening 14. In addition, reactants (i.e., etching residue) will be deposited on the bottom of the opening 14. Accordingly, if the over-etching is performed for a rather long time, then the ashing process will also be needed, thus causing deformation or damage as well.
Considering these potential disadvantages, it is not preferable to over-etch the insulating film 11 for the purpose of eliminating the ashing process using the oxygen plasma.
The same problems arise in the dual damascene process of the second prior art example, too. Specifically, when, the second resist pattern 27 is stripped by the ashing process using the oxygen plasma, the damaged layer 15 will be also formed by the oxygen plasma around the via hole 26 and/or interconnection groove 28 of the first and/or second insulating film(s) 21, 23. Or the first and/or second insulating film(s) 21, 23 will be partially deformed.
Also, as in the single damascene process, if the first and/or second insulating film(s) 21, 23 are/is over-etched during the plasma etching process, then the damaged layer will also be formed or the insulating film(s) 21, 23 will also be deformed partially.
These problems are even more serious for the dual damascene process. The reason will be described briefly. As shown in FIG. 23(b), if the opening 27a of the second resist pattern 27 is misaligned with the via hole 26, then part of the second resist pattern 27 will exist inside the via hole 26. Accordingly, even if the second resist pattern 27 is ashed using the oxygen plasma, a resist residue 27b of the second resist pattern 27 will still be left inside the via hole 26 and a damaged layer 29 will also be formed around the inner walls of the via hole 26 as shown in FIG. 23(c). In addition, the inner walls of the interconnection groove 28 will be dented inward and the width of its opening exceeds that of the opening of the second etch stopper film 24.
In that situation, the ashing process should be performed to remove the resist residue 27b or the over-etching process should be performed for a long time during the plasma etching process to avoid the formation of the resist residue 27b. However, in any case, the damage or deformation around the inner walls of the via hole 26 or interconnection groove 28 worsens.
Furthermore, an insufficient depth of focus is a problem commonly observable in the single and dual damascene processes. Specifically, a photolithographic process is needed to define a resist pattern. However, if the surface of an insulating film, which should be located under the resist pattern to be defined, is not flat enough, then a sufficient depth of focus cannot be attained during the exposure of the lithographic process. In that case, the resist pattern cannot be defined accurately, and fine via holes or interconnection grooves cannot be formed as intended.
An object of the invention to eliminate the resist residue from an insulating film in forming a via hole or interconnection groove through the insulating film by a single or dual damascene process, and prevent portions of the insulating film, surrounding the hole or groove, from being damaged or deformed.
To achieve this object, a first inventive method for fabricating a semiconductor device includes the steps of: a) depositing an organic insulating film over a semiconductor substrate; b) forming a silylated layer selectively on the organic insulating film; and c) etching the organic insulating film using the silylated layer as a mask, thereby forming an opening, which will be a via hole or interconnection groove, in the organic insulating film.
In the first method, an opening is formed by etching an organic insulating film using a silylated layer, which has been formed selectively on the organic insulating film, as a mask. Accordingly, no resist patterns are needed. That is to say, a resist-free process is realized and there is no need to perform the process step of ashing a resist pattern away or excessively over-etching the organic insulating film. Thus, the quality of the organic insulating film does not degrade and the inner walls of the opening are not damaged or deformed, either.
In one embodiment of the first method, the step b) preferably includes the steps of: terminating a surface of the organic insulating film with hydroxyls; selectively exposing the surface of the organic insulating film to a high-energy radiation, thereby removing the hydroxyls from exposed parts of the organic insulating film; and supplying a silylation reagent onto the selectively-exposed surface of the organic insulating film, thereby forming the silylated layer on the surface of non-exposed parts of the organic insulating film.
In such an embodiment, just the surface of the organic insulating film should be exposed to the high-energy beams but the deeper portions thereof need not. Thus, compared to the conventional resist process, a much greater margin is available for the depth of focus.
In another embodiment of the first method, the step b) may include the steps of: forming a layer to be silylated over the organic insulating film; selectively exposing a surface of the layer to be silylated to a high-energy radiation; supplying a silylation reagent onto the selectively-exposed surface of the layer to be silylated, thereby forming the silylated layer selectively in exposed or non-exposed parts of the layer to be silylated; and removing the exposed or non-exposed parts of the layer to be silylated, in which the silylated layer has not been formed.
In such an embodiment, just the layer to be silylated should be exposed to the high-energy beams. In addition, the layer to be silylated has only to be thick enough to resist the etching process of the organic insulating film. Thus, compared to the conventional resist process, a much greater margin is available for the depth of focus.
Moreover, since the silylated layer is formed selectively in exposed or non-exposed parts of the layer to be silylated that has been formed over the organic insulating film, the silylated layer can always be formed irrespective of the quality of the organic insulating film.
In still another embodiment, a porous insulating film may be used instead of the organic insulating film.
A second inventive method for fabricating a semiconductor device includes the steps of: a) depositing a first insulating film over a semiconductor substrate; b) forming a via hole through the first insulating film; c) depositing a second insulating film, which has an etch selectivity with respect to the first insulating film, over the first insulating film; d) forming a silylated layer selectively on the second insulating film; and e) etching the second insulating film using the silylated layer as a mask, thereby forming an interconnection groove through the second insulating film and removing part of the second insulating film that has been filled in the via hole.
In the second method, the opening is formed by etching the second insulating film using the silylated layer, which has been formed selectively on the second insulating film, as a mask. Accordingly, no resist patterns are needed. That is to say, a resist-free process is realized and there is no need to perform the process step of ashing a resist pattern away or excessively over-etching the second insulating film. Thus, the quality of the second insulating film does not degrade and the inner walls of the opening are not damaged or deformed, either.
A third inventive method for fabricating a semiconductor device includes the steps of: a) depositing a first insulating film over a semiconductor substrate; b) forming an etch stopper film over the first insulating film; c) forming a: via hole through the first insulating and etch stopper films; d) depositing a second insulating film over the etch stopper film; e) forming a silylated layer selectively on the second insulating film; and f) etching the second insulating film using the silylated layer as a mask, thereby forming an interconnection groove through the second insulating film and removing part of the second insulating film that has been filled in the via hole.
As in the second method, the opening is formed according to the third method by etching the second insulating film using the silylated layer, which has been formed selectively on the second insulating film, as a mask. As a result, a resist-free process is realized. Thus, the quality of the second insulating film does not degrade and the inner walls of the opening are not damaged or deformed, either.
A fourth inventive method for fabricating a semiconductor device includes the steps of: a) depositing a first insulating film over a semiconductor substrate; b) forming an etch stopper film over the first insulating film; c) forming a via hole through the etch stopper film; d) depositing a second insulating film over the etch stopper film; e) forming a silylated layer selectively on the second insulating film; and f) etching the second and first insulating films using the silylated layer as a mask, thereby forming an interconnection groove through the second insulating film and another via hole through the first insulating film so that the via holes of the etch stopper and first insulating films are connected together.
As in the second method, the opening is formed according to the fourth method by etching the second insulating film using the silylated layer, which has been formed selectively on the second insulating film, as a mask. As a result, a resist-free process is realized. Thus, the quality of the second insulating film does not degrade and the inner walls of the opening are not damaged or deformed, either.
A fifth inventive method for fabricating a semiconductor device includes the steps of: a) depositing a first insulating film over a semiconductor substrate; b) forming an etch stopper film over the first insulating film; c) forming a via hole through the first insulating and etch stopper films; d) forming a plug by filling in the via hole with a metal film; e) depositing a second insulating film over the plug and the etch stopper film; f) forming a silylated layer selectively on the second insulating film; and g) etching the second insulating film using the silylated layer as a mask, thereby forming an interconnection groove through the second insulating film.
As in the second method, the opening is formed according to the fifth method by etching the second insulating film using the silylated layer, which has been formed selectively on the second insulating film, as a mask. As a result, a resist-free process is realized. Thus, the quality of the second insulating film does not degrade and the inner walls of the opening are not damaged or deformed, either.
In the second through fifth inventive methods, the diameter of the via hole may be greater than the width of the interconnection groove.
In such an embodiment, the area of contact between a lower-level interconnect, which is located closer to the semiconductor substrate, and an inlaid interconnect, which has been formed out of a conductor film filled in the interconnection groove, does not decrease.
In the second through fifth inventive methods, the width of the interconnection groove may be greater than the diameter of the via hole.
In such an embodiment, the area of contact between a lower-level interconnect, which is located closer to the semiconductor substrate, and a via contact, which has been formed out of a conductor film filled in the via hole, does not decrease.
In the second through fifth inventive methods, the second insulating film may be an organic insulating film. And the step of forming the silylated layer may include the steps of: terminating a surface of the second insulating film with hydroxyls; selectively exposing the surface of the second insulating film to a high-energy radiation, thereby removing the hydroxyls from exposed parts of the second insulating film; and supplying a silylation reagent onto the selectively-exposed surface of the second insulating film, thereby forming the silylated layer on the surface of non-exposed parts of the second insulating film.
In such an embodiment, just the surface of the second insulating film should be exposed to the high-energy beams but the deeper portions thereof need not. Thus, compared to the conventional resist process, a much greater margin is available for the depth of focus.
In the second through fifth inventive methods, the second insulating film may be an organic insulating film. And the step of forming the silylated layer may include the steps of: forming a layer to be silylated on the second insulating film; selectively exposing a surface of the layer to be silylated to a high-energy radiation; supplying a silylation reagent onto the selectively-exposed surface of the layer to be silylated, thereby forming the silylated layer selectively in exposed or non-exposed parts of the layer to be silylated; and removing the exposed or non-exposed parts of the layer to be silylated, in which the silylated layer has not been formed.
In such an embodiment, just the layer to be silylated should be exposed to the high-energy beams, and the layer to be silylated has only to be thick enough to resist the etching process of the second insulating film. Thus, compared to the conventional resist process, a much greater margin is available for the depth of focus.
In the second through fifth inventive methods, at least one of the first and second insulating films is preferably a porous insulating film.
In such an embodiment, a dielectric constant between contacts formed in the first insulating film and/or a dielectric constant between inlaid interconnects formed in the interconnection grooves of the second insulating film can be decreased.
In the second inventive method, the first insulating film is preferably an inorganic insulating film, organic/inorganic hybrid film or CVD organic insulating film, while the second insulating film is preferably an organic insulating film.
In such an embodiment, an inlaid interconnect, which will be formed in the interconnection groove of the second insulating film, can have its dielectric constant lowered.
In the third through fifth inventive methods, the first insulating film is preferably an organic insulating film or organic/inorganic hybrid film, while the second insulating film is preferably an organic insulating film.
In such an embodiment, a dielectric constant between inlaid interconnects, which will be formed in the interconnection grooves of the second insulating film, can be decreased.
A sixth inventive method for fabricating a semiconductor device includes the steps of: a) depositing a first insulating film over a semiconductor substrate; b) forming a first silylated layer selectively on the first insulating film, c) etching the first insulating film using the first silylated layer as a mask, thereby forming a via hole through the first insulating film; d) depositing a second insulating film over the first silylated layer; e) forming a second silylated layer selectively on the second insulating film; and f) etching the second insulating film using the second silylated layer as a mask, thereby forming an interconnection groove through the second insulating film and removing part of the second insulating film that has been filled in the via hole.
In the sixth method, the via hole is formed by etching the first insulating film using the first silylated layer, which has been formed selectively on the first insulating film, as a mask. And the interconnection groove is formed by etching the second insulating film using the second silylated layer, which has been formed selectively on the second insulating film, as a mask. As a result, a resist-free process is realized. Thus, the quality of the first or second insulating film does not degrade and the inner walls of the via hole or interconnection groove are not damaged or deformed, either.
In one embodiment of the sixth method, the first and second insulating films may be organic insulating films. The step b) may include the steps of: terminating a surface of the first insulating film with hydroxyls; selectively exposing the surface of the first insulating film to a high-energy radiation, thereby removing the hydroxyls from exposed parts of the first insulating film; and supplying a silylation reagent onto the selectively-exposed surface of the first insulating film, thereby forming the first silylated layer on the surface of non-exposed parts of the first insulating film. And the step e) may include the steps of: terminating a surface of the second insulating film with hydroxyls; selectively exposing the surface of the second insulating film to a high-energy radiation, thereby removing the hydroxyls from exposed parts of the second insulating film; and supplying a silylation reagent onto the selectively-exposed surface of the second insulating film, thereby forming the second silylated layer on the surface of non-exposed parts of the second insulating film.
In such an embodiment, just the surface of the first or second insulating film should be exposed to the high-energy beams but the deeper portions thereof need not. Thus, compared to the conventional resist process, a much greater margin is available for the depth of focus.
In another embodiment of the sixth method, the first and second insulating films may be organic insulating films. The step b) may include the steps of: forming a first layer to be silylated on the first insulating film; selectively exposing a surface of the first layer to be silylated to a high-energy radiation; supplying a silylation reagent onto the selectively-exposed surface of the first layer to be silylated, thereby forming the first silylated layer selectively in exposed or non-exposed parts of the first layer to be silylated; and removing the exposed or non-exposed parts of the first layer to be silylated, in which the first silylated layer has not been formed. And the step e) may include the steps of: forming a second layer to be silylated on the second insulating film; selectively exposing a surface of the second layer to be silylated to a high-energy radiation; supplying a silylation reagent onto the selectively-exposed surface of the second layer to be silylated, thereby forming the second silylated layer selectively in exposed or non-exposed parts of the second layer to be silylated; and removing the exposed or non-exposed parts of the second layer to be silylated, in which the second silylated layer has not been formed.
In such an embodiment, just the first or second layer to be silylated should be exposed to the high-energy beams. In addition, the first or second layer to be silylated has only to be thick enough to resist the etching process of the first or second insulating film. Thus, compared to the conventional resist process, a much greater margin is available for the depth of focus.
In yet another embodiment, at least one of the first and second insulating films is preferably a porous insulating film.
In such an embodiment, a dielectric constant between contacts formed in the first insulating film and/or a dielectric constant between inlaid interconnects formed in the interconnection grooves of the second insulating film can be decreased.